At the time of manufacturing a thin film transistor, it is required to guarantee the precision of alignment between multilayer films. FIG. 1 is a structural schematic diagram of the prior art thin film transistor. The prior art thin film transistor mainly comprises a gate layer 01, a source 02 and a drain 03 located on the gate layer 01 and an active layer 04 located on the source 02 and the drain 03. Upon manufacture, it is required to guarantee the precision of alignment between the gate layer 01, the source 02, the drain 03 and the active layer 04, so as to ensure that the ratio of width W (illustrated by a bold line in FIG. 1) to length of the channel formed upon electrifying is unchanged.
However, at the time of manufacturing the prior art thin film transistor, it is difficult to guarantee the precision of alignment between the gate layer, the source, the drain and the active layer. When there is alignment deviation between the source, drain and the active layer, the width W of the channel will change such that the ratio of width to length of the channel will be changed, thereby influencing the picture display effect of the display device.